The present invention relates generally to semiconductor device manufacturing and, more particularly, to silicon-on-insulator (SOI) transistors having improved extension resistance and channel strain characteristics.
Complementary metal oxide semiconductor (CMOS) field effect transistors (FETs) are employed in almost every electronic circuit application including, for example, signal processing, computing, and wireless communications. SOI transistors are those devices in which the active device area (including the FET channel) is formed in a relatively thin layer of silicon (or other semiconducting material) disposed over a buried insulating layer (such as an oxide, in which case the buried insulating layer is called a BOX). The buried insulating layer is in turn formed over a bulk (e.g., silicon) substrate. An advantage of SOI devices is the reduction of cross talk with other transistor devices, as well as the reduction of parasitic capacitance.
As transistor devices continue to scale, a reduction in FET gate size has also led to a decrease in the thickness of the SOI layer in order to control short channel effects. In fact, the so-called extremely thin SOI or ETSOI devices can have SOI thicknesses on the order of about 10 nanometers (nm) or less. On the other hand, such thin SOI devices lead to higher source/drain extension resistances, which may be mitigated to a certain extent by forming raised source/drain regions.
However, another obstacle to maintaining lower source/drain extension resistances in ETSOI devices is the loss of dopants due to diffusion through the ETSOI and into the BOX with conventional dopant activation processes. Moreover, there is also the problem of maintaining desirable channel strain properties in ETSOI devices, as it is well known that a tensile stress applied to a channel of an NFET device and a compressive stress applied to a channel of a PFET device increases the respective carrier mobilities thereof.